Transistors are prone to damage from electrostatic discharges (ESD's).
A transistor electrode is typically connected via a series of contacts to a semiconductor substrate. In the event of an ESD, the excess current may discharge through the substrate via the series of contacts. A contact of the series nearest the edge of the substrate may draw a larger current than the other contacts in the series because at the edge there is a greater surface area through which current may flow. This excessive current flow may damage the contact nearest the edge of the substrate. A further problem is that typically at the edge an inherently weak insulation exists between a polycrystalline gate of the transistor and the substrate. ESD's have been known to result in a short circuit therebetween.
This invention seeks to provide a voltage protection arrangement in which the above mentioned disadvantages have been mitigated.